In recent years, with the rapid development of new energies and distributed power generation technologies, multi-level inverters, particularly three-level inverters and five-level inverters, have been widely used. In practice, the control of a multi-level inverter is usually realized through a pulse-width modulation (PWM) technology, where the required number of PWM pulse outputs increases with the increasing number of levels of the inverter and so does the complexity of the corresponding method of generating PWM pulses.
In the conventional art, PWM peripheral units of a C2000 Series DSP (Digital Signal Processing) chip are used for the determination of increase or decrease of the triangular carrier wave and the control of the duty ratio, to output corresponding PWM pulse signals. The PWM peripheral units of the DSP chip in this series have 12 PWM outputs in total.
For a three-phase three-level inverter with 12 switches, in a case that all the PWM peripheral units of the DSP chip are used, it can output PWM pulses required by the three-phase three-level inverter, but the number of levels of the inverter can not be increased. For an inverter with more levels, such as a three-phase five-level inverter with 24 switches, the DSP chip in this series can not output sufficient PWM pulses for the three-phase five-level inverter.
Therefore, for an multi-level inverter that has a wide application at present, it is an urgent problem to be solved that how to ensure both the reliable output of PWM pulses and the effective saving of PWM peripheral units of a DSP chip to reduce the difficulty in increasing the number of levels of the inverter.